Among dynamic-type semiconductor memory devices that require refreshing for data retention, there is known the semiconductor memory device in which an on-chip ECC (Error Correction Circuit) is included therein. In these devices, when a data retention operating mode is entered by input of an entry command to enter into the data retention operating mode, the ECC performs encoding (parity bit generation) on all bits in a memory cell array. Then, as an exit operation through input of an exit command, decoding (error correction) on all the bits is performed, thereby extending a refresh cycle and reducing a data retention current more than the capability of the device (capability such as a data retention characteristic or the like) (refer to Patent Documents 1 and 2, for example). Such a data retention operating mode is referred to as a “Super Self Refresh mode” (abbreviated as the “SSR mode”) herein. For details of the ECC (an ECC-CODEC) in a semiconductor integrated circuit device having the “SSR mode” and state transitions in the SSR mode, Patent Documents 1 and 3, and the like, for example, will be referred to.
An example of an operation of the SSR mode, as a prerequisite for the present invention, will be described with reference to FIGS. 1 and 2. FIG. 1 is a diagram showing an example of a typical configuration of the semiconductor memory device provided with the ECC-CODEC that includes an encoding circuit and a decoding circuit as the ECC and an ECC controller. The present invention is suitably applied to the configuration shown in FIG. 1, to which a reference is made in the description of embodiments of the present invention.
Referring to FIG. 1, this semiconductor memory device (or the semiconductor integrated circuit device provided with the semiconductor memory device) is an SDRAM (Synchronous Dynamic Random Access Memory: referred to as the “SDRAM”). In this SDRAM 10, though no specific limit is placed thereon, four memory arrays (MEMORY ARRAYs) 200A to 200D are provided corresponding to four memory banks (BANKs 0 to 3). Each of the memory arrays 200A to 200D corresponding to the four memory banks 0 to three (BANKs 0 to 3) includes dynamic-type memory cells arranged in a matrix form. Then, in each memory array, gate terminals of memory cell transistors not shown are connected to word lines (not shown), ones of drains and sources of the memory cell transistors are connected to complementary bit lines (not shown) for respective rows, and the others of the drains and sources are connected to one ends of capacitor elements for data storage. According to a result of decoding of a row address signal by a row decoder (ROW DECODER & LATCH) 201, a word driver (WORD DRIVER) 202 drives a selected word line (not shown) in the bank0 memory array 200A to a high potential. The complementary bit lines (not shown) in the memory array 200A are connected to IO lines by sense amplifiers (SENSE AMPLIFIERS) 203, I/O gating write drivers (I/O GATING WRITE DRIVERS) 204 and a column decoder (COLUMN DECORDER) 205 as a column selection circuit. A main amplifier and a write amplifier are included in each I/O gating write driver 204.
Each of the sense amplifiers 203 receives and detects a minute potential difference resulting from data reading from a selected memory cell on each pair of the complementary bit lines to amplify the potential difference. The I/O gating write drivers 204 includes column switch MOS transistors for selecting the complementary bit lines and electrically connecting the complementary bit lines to the complementary I/O lines. A column switch MOS transistor is selected for operation according to the result of decoding of a column address signal by the column address decoder. Likewise, for the memory arrays 200B-200D in the banks 1 through 3, the row decoder (ROW DECODER & LATCH), sense amplifiers (SENSE AMPLIFIERS), I/O gating write drivers (I/O GATING WRITE DRIVERS), and column decoder (COLUMN DECODER) are provided.
The I/O lines are made to be common to the respective memory banks, and are connected to the output terminal of a data input register (DATA INPUT REGISTER) 210 and the input terminal of a data output register (DATA OUTPUT REGISTER) 211. Terminals DQ0 to DQ15 (for 16 bits) are data input/output terminals, and are the data input/output terminals for inputting or outputting data D0 to D15 (a low-order byte D0 to D7 and a high-order byte D8 to D15). DQML and DQMU are control signals for byte control for controlling input/output buffers. The DQML controls the input buffer for the lower-order byte, while the DQMU controls the input buffer for the higher-order byte.
Bits A0 to A12 of 15-bit address signal supplied from an address input terminal are temporally held in an address register (ADD REG) 213. Among the address signals input sequentially, a row-address signal for selecting a memory cell is supplied to the row decoder 201 of each memory bank through a row address multiplexer (ROW ADD MUX) 206. A13 and A14 are assigned to BA0 and BA1 for selecting the memory bank described above, and are supplied to a bank control logic (BANK CONTROL LOGIC) circuit 212, where a selection signal for performing selection among the four memory banks described above is formed, and supplied to the row decoder 201. A column-address signal is held in a column-address counter/latch (COLUMN-ADDRESS COUNTER/LATCH) 207.
A refresh counter (REFRESH. COUNTER) 208 generates a row address for a self refresh (Self Refresh). When a storage capacity of 256 Mbits is included, for example, and in the case of an x8-bit configuration, an address signal of nine bits are made to be effective as the column address signal. To the column address counter 207, the column address signal input sequentially is supplied as preset data. Then, in a burst mode specified by a command which will be described hereinafter, the column address signal as the preset data or a value obtained by sequentially incrementing the column address signal is output to the column decoder 205 of each memory bank.
A control logic (CONTROL LOGIC) 209 constitutes a circuit for an SDRAM interface, and includes a command decode (COMMAND DECODE) circuit 2091, a self-refresh control (SELF-REF CONTROL) 2092, and a mode register (MODE REGISTER) 2093. The mode register 2093 holds information on various operating modes (such as a burst length and CAS latency information) for the semiconductor memory device.
The command decode circuit 2091 receives an external command and an internal command according to an operating mode, for decoding.
The self-refresh control circuit 2092 is a control block for the self refresh, and performs a refreshing operation and executes its cyclic control.
Only the row decoder 201 corresponding to the bank specified by the bank control logic circuit (BANK CONTROL LOGIC) 212 operates and performs a word line selecting operation.
In an example shown in FIG. 1, to the control logic 209, external control signals such as a clock signal CLK, a clock enable signal CKE, a chip select signal CS, a column address strobe signal CAS, a row address strobe signal RAS, and a write enable signal WE, a DQM (DQ mask: for controlling the high impedance state of the output buffer of a DQ terminal), and the address signal through the mode register 2093 are supplied. The control logic 209 generates internal timing signals for controlling the operation of circuit blocks described above and the operating mode of the SDRAM based on a change in the levels of these signals and timings of these signals and includes input buffers (not shown) for the respective signals. Other external input signals are made to be significant in synchronization with the rising edge of the internal clock signal. The chip select signal CS at its low level commands a start of a command input cycle. When the chip select signal CS is at a high level (or a chip non-selection state), other inputs are not significant. However, a memory bank selection state and an internal operation such as a burst operation are not influenced by a change to the chip non-selection state. Functions of the respective signals such as the RAS, CAS, and WE are different from those of the corresponding signals in ordinary DRAMs, and these signals are made to be significant when a command cycle is defined.
The clock enable signal CKE is the signal to instruct effectiveness of the subsequent clock signal CLK. The clock enable signal CKE at the high level indicates that the rising edge of the subsequent clock signal CLK is effective. The clock enable signal CKE at the low level indicates that the rising edge of the subsequent clock signal CLK is ineffective.
The row address signal is defined by the levels of the A0 to A12 in a row address strobe and bank active command cycle that is synchronized with the rising edge of the clock signal CLK (an internal clock signal ICLK not shown, generated from the CLK).
The address bits A13 and A14 (the BA0 and BA1 in FIG. 1) are regarded as a bank selection signal in the row address strobe and bank active command cycle. That is, by a combination of the BA0 and the BA1, one of the four memory banks 0 to 3 is selected. Control over memory bank selection can be performed by processing such as activation of only the row decoder of a selected memory bank, no selection of any column switch circuits of unselected memory banks, and connection to only the data input circuit 210 and a data output circuit of the selected memory bank. Assume that while the burst operation is performed in one memory bank, another memory bank is designated and a row address strobe and bank active command is supplied in the SDRAM. Then, the operation of a row address system in the another memory bank becomes possible with no influence exerted on the operation of the memory bank in which the burst operation is being executed. Accordingly, as long as there is no data collision at the data input/output terminals DQ0 to DQ 15 for data constituted from 16 bits, during execution of a command on which processing has not been finished, it is possible to issue a precharge command, and the row address strobe and bank active command for a memory bank different from a memory bank targeted for processing by the command being executed can be issued and to start an internal operation in advance.
Referring to FIG. 1, reference numeral 1 denotes a signal supplied from the SDRAM interface, for starting and stopping an ECC controller 6.
Reference numeral 2 denotes an internal command signal or a JOB completion signal for the SDRAM interface, supplied from the ECC controller 6. When an encoding operation or a decoding operation is completed, for example, a READY signal is output.
Reference numeral 3 denotes an internal address signal supplied from the ECC controller 6 to an address register 213.
Reference numeral 4 denotes an operating mode signal for an ECC encoding and decoding circuit (ECC-CODEC) 7. The signal is controlled from the ECC controller 6 according to an operation.
Reference numeral 5 denotes an error detection signal or an error location detection signal (ERROR LOCATION) from the ECC-CODEC (encoding and decoding circuit) 7 to the ECC controller 6.
Reference numeral 6 denotes the ECC controller (one set/four banks). An internal command and an internal address are output from the ECC controller 6, thereby controlling the internal operation of the SDRAM and also controlling the ECC-CODEC (codec) 7 according to an operation.
Reference numeral 7 denotes the ECC-CODEC, which includes the encoding circuit and the decoding circuit. The ECC-CODEC performs a syndrome calculation, parity bit calculation, and error detection and correction.
Reference numeral 14 denotes the memory array of a bank memory, reference numeral 15 denotes a parity region. Parity information of memory cell data calculated by the ECC-CODEC 7 is stored in the parity region 15.
A cyclic code (Cyclic Code) is employed for the ECC (for error detection and correction) mounted on chip on a DRAM, and implements reduction of a standby current resulting from correction (masking) of a faulty refresh at the time of a self refresh. When the cyclic code is applied for the ECC, the circuit size of the encoding/decoding (CODEC) circuit that constitutes the ECC is also reduced. Thus, a code length can be increased, the number of parity bits can be reduced, and an increase in the chip area due to the on-chip ECC for the DRAM can be minimized.
As described above, due to the SSR mode, the semiconductor memory device includes the ECC controller 6 and the EC-CODEC 7 (including the encoding circuit for generating parity bits from original memory data and the decoding circuit for generating error-corrected memory data from the parity bits and read data from the memory). The ECC controller 6 issues an internal command 2 and an internal address 3 to the SDRAM 10 by itself. The command decode circuit (COMMAND DECODE) 2091 is configured to receive both the external command and the internal command 2. The ECC controller 6 issues the operating mode control signal 4 for the CODEC as a control command to the ECC-CODEC 7, and receives the error detection (ERROR)/error location detection (LOCATION) signal 5 from the ECC-CODEC 7 to perform a parity bit generation and writing operation and an error correcting operation efficiently.
Next, referring to FIG. 2, an example of a typical operation in the SSR (Super Self-Refresh) mode in the semiconductor memory device in FIG. 1 will be outlined. In the semiconductor memory device shown in FIG. 1, the command decode circuit (COMMAND DECODE) 2091 of the control logic (CONTROL LOGIC) 209 of the SDRAM 10 decodes the external command constituted from a combination of the signals CKE, CS, WE, CAS, and RAS. Then, when it is found that the command is the command to enter into the SSR mode (SSELF: refer to a third signal waveform “External Operation” from the top in FIG. 2), the command decode circuit 2091 sends a start (START) command signal (ENCODE) to the ECC controller 6 as the control signal 1.
The start command signal (ENCODE) is shown as a rise of a fourth signal waveform “ENCODE” from the top in FIG. 2.
Supply of the external clock signal CLK to the SDRAM 10 is stopped at a point of time when the command decode circuit (COMMAND DECODE) 2091 has received the SSR entry command (SSELF)(refer to a second signal “CLK” from the top in FIG. 2).
When the ECC controller 6 receives the start command signal (ENCODE), the internal clock signal ICLK (refer to the “ICLK” in FIG. 2) is supplied to the ECC controller 6. The ECC controller 6 sends out an “encoding” command to the ECC-CODEC 7 as the operating mode control signal 4.
Upon receipt of the “encoding” command as the operating mode control signal 4, the ECC-CODEC 7 starts an encoding operation. That is, the ECC-CODEC 7 generates parity data (check bits for error detection and correction) based on information data held by each bank in the memory, and writes the generated data in the parity memory region (PARITY indicated by reference numeral 15 in FIG. 1) of each bank in the memory (refer to “Parity Generation with Refresh” in an “Internal Operation” in the lowest line in FIG. 2).
When the generation of the parity data and the writing of the generated data in the parity memory region (PARITY) by the ECC-CODEC 7 have been completed, the ECC controller 6 outputs the completion signal READY (refer to the second “READY” from the bottom in FIG. 2) to the command decode circuit (COMMAND DECODE) 2091 as the internal command 2.
When the command decode circuit (COMMAND DECODE) 2091 receives the completion signal READY as the internal command 2 and decodes the signal, the command decode circuit 2091 stops supply of the start command signal ENCODE (refer to FIG. 2) to the ECC controller 6. Supply of the internal clock ICLK to the ECC controller 6 is also stopped (refer to the “ICLK” in FIG. 2).
When the command decode circuit (COMMAND DECODE) 2091 receives the completion signal READY as the internal command 2 and decodes the signal, the self-refresh control circuit 2092 of the control logic (CONTROL LOGIC) 209 starts a “Super Self-Refresh” (super self-refresh) operation in FIG. 2. In this “Super Self-Refresh” operation, an internal power supply for turning off a part of an internal power supply circuit are turned off (a “POFF” state: refer to the “Internal Operation” in the lowest line in FIG. 2), the power supply turned-off state is maintained for a predetermined period (such as 10 seconds), the internal power supply circuit in the off state is then recovered, the internal power supply is turned on (a “PON” state: refer to the “Internal Operation” in FIG. 2), and then a normal refresh (a “Burst-Refresh”: refer to the “Internal Operation” in the lowest line in FIG. 2) is carried out. Then, the “POFF”, “PON”, and “Burst-Refresh” are repeated arbitrary times. In the “Burst-Refresh”, all words in the memory cell array are intensively refreshed in a cycle shorter than in an ordinary self refresh. However, error correction based on the parity data is not carried out.
When the command to enter into the SSR mode (SSELF) is fed to the command decode circuit 2091 during an ordinary operation (in an idle state) and the SSR mode is entered, as described above, the ENCODE signal is activated, so that processing for the parity data generation and writing of the generated parity data in the parity region 15 (“Parity Generation with Refresh”) is performed (the foregoing description refers to the processing in an “ENTRY-TIME”). Then, together with the operation of turning off the power supply, the “Super Self-Refresh” operation is performed. In accordance with the turning off of an internal signal source, most of the internal power supply (such as the cell array unit (having a boost potential VPP, a substrate potential VBB, and the like)) and an internal power supply generation circuit for a peripheral circuit unit are turned off (to 0v: a ground potential), so that the memory is entered into the state of a long-period pause state (a wait with the internal power supply circuit stopped).
Then, as shown in FIG. 2, an internal signal GSTATE is generated, which indicates that the supply potential of the internal power supply circuit has risen completely.
When the signal GSTATE undergoes a transition from a low level to a high level during a “Super Self-Refresh” period, i.e., when the power is turned on again, the operation of the “Burst-Refresh” (burst-refresh) for continuously performing a refresh on all the cells is performed.
After the operations of turning off the internal power supply (POFF), the long-period pause, turning on the internal power supply (PON), and the burst-refresh (Burst-Refresh) are repeated the arbitrary times (operations in the “Super Self-Refresh”), an SSR exit command (SSELFX) is entered, so that the SSR mode is ended. A memory cell data error generated by the influence of the long-period pause of the refresh is corrected and rewriting (refer to “Correct with Refresh” of the “Internal Operation” in FIG. 2) is executed (processing in an “EXIT-TIME”). That is, the command decode circuit (COMMAND DECODE) 2091 of the control logic (CONTROL LOGIC) 209 in the SDRAM 10 decodes the external command constituted from the combination of the signals CKE, CS, WE, CAS, and RAS. When it is found that the external command is the SSR exit command (SSELFX: refer to the “External Operation” in FIG. 2), the command decode circuit (COMMAND DECODE) 2091 sends out a stop (STOP) command signal (DECODE) to the ECC controller 6 as the control signal 1. That is, the stop command signal (DECODE) (refer to the “DECODE” in FIG. 2) is activated (made high). When the ECC controller 6 receives the stop command signal (DECODE), the internal clock signal ICLK (refer to FIG. 2) is supplied, and a “decode” command is sent out to the ECC-CODEC 7 as the operating mode control signal 4.
When the ECC-CODEC 7 receives the “decode” command as the operating mode control signal 4, the ECC-CODEC 7 starts a decoding operation. That is, the ECC-CODEC 7 reads out the parity data and also corrects an information data error based on the parity data and information data held by the memory, and performs rewriting. The error correction and the rewriting are performed on all the cells in a memory region. When the error correction and the rewriting by the ECC-CODEC 7 is finished, the ECC controller 6 outputs the completion signal (READY) to the command decode circuit (COMMAND DECODE) 2091 as the internal command 2.
When the command decode circuit (COMMAND DECODE) 2091 receives the completion signal READY as the internal command 2 for decoding, the command decode circuit stops supply of the stop command signal DECODE to the ECC controller 6. Supply of the internal clock signal ICLK to the ECC controller 6 is also stopped.
With this arrangement, the semiconductor memory device exists from the SSR mode, and returns to a normal operation (a normal “Self-Refresh” operation in the case of FIG. 2). During the decode processing at the time of the exit, a self refresh (distributed refresh: Distributed Refresh) is performed as necessary.
As a semiconductor device equipped with the output function of flag information, a configuration in which the information is detected by a temperature sensor and the information is output from a flag pin is described in Patent Document 3, for example.
[Patent Document 1]
                JP Patent Kokai Publication No. JP-P2004-152378A[Patent Document 2]        JP Patent Kokai Publication No. JP-P2002-056671A[Patent Document 3]        JP Patent Kokai Publication No. JP-P2003-68076A[Patent Document 4]        U.S. Pat. No. 6,373,768        